A DIGITAL NEURAL-NETWORK COPROCESSOR WITH A DYNAMICALLY RECONFIGURABLE PIPELINE ARCHITECTURE

Authors
MORISHITA T TAMURA Y SATONAKA T INOUE A KATSU S OTSUKI T
Citation
T. Morishita et al., A DIGITAL NEURAL-NETWORK COPROCESSOR WITH A DYNAMICALLY RECONFIGURABLE PIPELINE ARCHITECTURE, IEICE transactions on electronics, E76C(7), 1993, pp. 1191-1196
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEICE transactions on electronics → ACNP
ISSN journal
09168524
Volume
E76C
Issue
7
Year of publication
1993
Pages
1191 - 1196
Database
ISI
SICI code
0916-8524(1993)E76C:7<1191:ADNCWA>2.0.ZU;2-#
Abstract
We have developed a digital coprocessor with a dynamically reconfigura ble pipeline architecture specified for a layered neural network which executes on-chip learning. The coprocessor attains a learning speed o f 18 MCUPS that is approximately twenty times that of the conventional DSP. This coprocessor obtains expansibility in the calculation throug h a larger multi-layer network by means of a network decomposition and a distributed processing approach.