A PROGRAMMABLE PARALLEL DIGITAL NEUROCOMPUTER

We developed programmable high-performance and high-speed neurocompute r for a large neural network using ASIC neurocomputing chips made by C MOS VLSI technology. The neurocomputer consists of one master node and multiple slave nodes which are connected by two data paths, a broadca st bus and a ring bus. The nodes are made by ASIC chips and each chip has plural nodes in it. The node has four types of computation hardwar e that can be cascaded in series forming a pipeline. Processing speed is proportional to the number of nodes. The neurocomputer is built on one printed circuit board having 65 VLSI chips that offers 1.5 billion connections/sec. The neurocomputer uses SIMD for easy programming and simple hardware. It can execute complicated computations, memory acce ss and memory address control, and data paths control in a single inst ruction and in a single time step using the pipeline. The neurocompute r processes forward and backward calculations of multilayer perceptron type neural networks, LVQ, feedback type neural networks such as Hopf ield model, and any other types by programming. To compute neural comp utation effectively and simply in a SIMD type neurocomputer, new proce ssing methods are proposed for parallel computation such as delayed in struction execution, and reconfiguration.