MULTIPLIER-FREE REALIZATIONS FOR FIR MULTIRATE CONVERTERS BASED ON MIXED-RADIX NUMBER REPRESENTATION

We propose some realizations of FIR multirate converters, They are bas ed on mixed-radix signed-digit number representation in conjunction wi th periodically time-varying (PTV) coefficients. These realizations ha ve desirable properties of low complexity and regularity with simple p rocessing elements that are suitable for easy VLSI layout. By varying some parameters, these realizations also provide a tradeoff between ha rdware and clock speed (or throughput). The PTV coefficients are restr icted to the set {0.+/-1} or {0.+/-1.+/-2} so that hardware multiplier s are not needed. The coefficient precision of these proposed structur es can be made as high as desired by appropriate choices of the parame ters. However, the disadvantage is that a more complex timing control is required. Several examples are presented,.