1ST LEVEL CALORIMETER TRIGGER SYSTEM FOR THE LARGE HADRON COLLIDER

As part of an R&D project to study first-level calorimeter triggers fo r LHC, we have designed an Application Specific integrated Circuit (AS IC) which will search for candidate electromagnetic (EM) clusters asso ciated with a particular cell from a 4 x 4 area of the calorimeter. Th e ASIC takes in sixteen (4 x 4) 8-bit digitised signals from the calor imeter and will provide two results: (i) A flag to indicate the presen ce of an EM cluster. (ii) A sum over the 4 x 4 area which will be used in the subsequent logic in the trigger system to search for jets and to calculate missing transverse energy. In LHC the bunch-crossing peri od is 15ns, and therefore the logic is implemented on the ASIC using a pipelined architecture, with pipeline steps of 15ns. The algorithm ha s been implemented on a 0.8 micron CMOS gate array, and is packaged in a 179 pin ceramic Pin Grid Array. The ASIC has been tested above the full operating frequency of 67 MHz.