We present results from an on-going program to test the performance of
high speed analog to digital converters suitable for use at the. SSC
and LHC colliders. For each device we have measured a large number of
parameters such as number of effective bits, noise level, aperture jit
ter, nonlinearity, analog bandwidth, and total harmonic distortion. In
this report, present results from a variety of eight- and ten-bit dev
ices. We will continue this work, extending it to twelve-bit devices a
s they become available.