DESIGNING OPTIMUM ONE-LEVEL CARRY-SKIP ADDERS

We show how to design one-level carry-skip adders that attain very hig h speeds in practice. One-level carry-skip adders are very fast adders that are hardly more complex than the much-slower ripple adders. Our design procedure allows the use of realistic component delays obtained by simulation, and is technology-independent. An example of a 64-bit, 1 mum CMOS adder is given, which achieves an add time of 6.23ns, meas ured by SPICE simulation with realistic loads. This delay figure exclu des sum buffering delays, which depend on the particular application o f the adder. The combination of high-speed and simplicity makes one-le vel carry-skip adders attractive for applications in highly parallel s ystems.