A 9.6-GB S HEMT ATM SWITCH LSI WITH EVENT-CONTROLLED FIFO/

Citation
Y. Watanabe et al., A 9.6-GB S HEMT ATM SWITCH LSI WITH EVENT-CONTROLLED FIFO/, IEEE journal of solid-state circuits, 28(9), 1993, pp. 935-940
Citations number
9
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
00189200
Volume
28
Issue
9
Year of publication
1993
Pages
935 - 940
Database
ISI
SICI code
0018-9200(1993)28:9<935:A9SHAS>2.0.ZU;2-5
Abstract
An asynchronous-transfer-mode (ATM) switch LS] has been designed for t he Broadband Integrated Services Digital Network (B-ISDN) and fabricat ed using 0.6-mum HEMT technology. To enhance the high-speed performanc e of direct-coupled FET logic (DCFL), we used event-controlled logic i nstead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8 x 4.7-mm2 chip contains 7100 DCFL gates. The maximum operation frequency was 1.2 GHz at room temperature with a pow er dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An e xperimental 4-to-4 ATM switching module using 16 switch LSI's achieved a throughput of 38.4 Gb/s.