AN OPTIMUM CMOS SWITCHED-CAPACITOR ANTIALISING DECIMATING FILTER

An optimum switched-capacitor (SC) decimating filter is capable of ach ieving a high input sampling frequency while the time period for the s ettling of the operational amplifiers can be maximized with respect to the lower output sampling frequency. Thus, for the same speed of the operational amplifiers, the oversampling ratio of the input signal in optimum SC decimating filters is much larger than in conventional SC f iltering circuits yielding a significant relaxation of the continuous- time prefiltering requirements. This is demonstrated considering the d esign of a second-order SC antialiasing decimating filter, with a thre efold sampling rate reduction, which has been realized in a 1.8-mum CM OS double-poly technology. The experimental evaluation of prototype sa mples confirms the expected operation of the circuit.