DESIGN-FOR-TEST STRUCTURE TO FACILITATE TEST VECTOR APPLICATION WITH LOW PERFORMANCE LOSS IN NON-TEST MODE

A switching based circuit is described which allows application of vol tage test vectors to internal nodes of a chip without the problem of b ackdriving. The new circuit has low impact on the performance of an an alogue circuit in terms of loss of bandwidth and allows simple applica tion of analogue test voltages into internal nodes. The circuit descri bed facilitates implementation of the forthcoming IEEE 1149.4 DfT phil osophy [1].