3-WEIGHT PSEUDORANDOM TEST-GENERATION BASED ON A DETERMINISTIC TEST SET FOR COMBINATIONAL AND SEQUENTIAL-CIRCUITS

A method for weighted pseudo-random test generation based on a determi nistic test set is described. The main advantages of the method descri bed over existing methods are: (1) only three easily generated weights -0, 0.5 and 1-are used, (2) a minimum number of shift register cells i s used, thus leading to minimal hardware for Built-In-Test application s, and (3) the weights are selected to allow the same coverage of targ et faults attained by the deterministic test set, to be attained by we ighted random patterns. The weights are computed by walking through th e range of test generation approaches from pure random at one extreme to deterministic at the other extreme, dynamically selecting the weigh t assignments to correspond to the remaining faults at every stage. Ha rdware suitable for the generation of random patterns under the propos ed method is described. The method is suitable for both combinational and sequential circuits. Experimental results are provided for ISCAS-8 5 and MCNC benchmark circuits.