DESIGN OF A PIPELINED RADIX-4 CORDIC PROCESSOR

In this work we develop a generalization of the CORDIC algorithm for a ny radix in three coordinate systems, linear, circular and hyperbolic. We carry out a comparative study between different radixes at the num ber of additions level, due to the fact that the complexity in additio ns determines the total hardware associated with the implementation of the algorithm. Radix 4 minimizes the number of additions, therefore w e propose a high speed CORDIC processor based on this radix 4. We have developed new criteria for the vectorization and rotation modes and w e introduce a new technique for the compensation of a non-constant sca le factor, multifactor compensation. The processor we propose is of a general and pipelined character and uses redundant arithmetic (signed digit) in order to reduce the delay in each stage, parallelizing the o peration of the adders using a competititive implementation (reduction of the number of stages) with respect to radix 2 implementations whic h have recently appeared in the literature.