BICMOS CIRCUIT TECHNIQUES FOR 3.3-V MICROPROCESSORS

With increases in frequency and density of RISC microprocessors due to rapid advances in architecture, circuit and fine device technologies, power consumption becomes a bigger concern. Supply voltage should be reduced from 5 V to 3.3 V. In this paper, several novel circuits using 0.5 mum BiCMOS technology are proposed. These can be applied to a sup erscalar RISC microprocessor at 3.3 V power supply or below. High spee d and low power consumption characteristics are achieved in a floating -point data path, an integer data path and a TLB by using the proposed circuits. The three concepts behind the proposed high speed circuit t echniques at low voltage are summarized as follows. There are a number of heavy load paths in a microprocessor, and these become critical pa ths under low voltage conditions. To achieve high speed characteristic s under heavy load conditions without increasing circuit area, low vol tage swing operation of a circuit is effective. By exploiting the high conductance of a bipolar transistor, instead of using an MOS transist or, low swing operation can be got. This first concept is applied to a single-ended common-base sense circuit with low swing data lines in t he register file of a floating and an integer data path. Both multi-se ries transistor connections and voltage drops by V(th) of MOS transist ors and V(be) of bipolar transistors also degrade the speed performanc e of a circuit. Then the second concept employed is a wired-OR logic c ircuit technique using bipolar transistors which is applied to a compa rator in the TLB instead of multi-series transistor connections of CMO S circuits. The third concept to overcome the voltage drops by V(th) a nd V(be) is addition of a pull up PMOS to both the path logic adder an d the BiNMOS logic gate to ensure the circuits have full swing operati on.