A 10-B 300-MHZ INTERPOLATED-PARALLEL A D CONVERTER/

This paper describes a monolithic 10-b A/D converter that realized a m aximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transist or V(bc) matching can be alleviated drastically, which improves differ ential nonlinearity (DNL) significantly to within +/-0.4 LSB. Furtherm ore, an extremely small input capacitance of 8 pF can be attained, whi ch translates into better dynamic performance such as SNR of 56 dB and THD of -59 dB for an input frequency of 10 MHz. Additionally, the fol ded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequentl y, the A/D converter has been implemented as a 9.0 x 4.2-mm2 chip inte grating 36K elements, which consumes 4.0 W using a 1.0-mum-rule, 25-GH z f(t). double-polysilicon self-aligned bipolar technology.