AN 8-B 85-MS S PARALLEL PIPELINE A/D CONVERTER IN 1-MU-M CMOS/

A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADC's) is presented. A prototype has be en designed consisting of four switched-capacitor (S/C) multistage pip elined ADC's in parallel. Hardware cost is minimized by sharing resist or strings, bias circuitry, and clock generation circuitry over the ar ray. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismat ches across the array. A key circuit issue is the design of a high-spe ed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode op-amp topology is used. An experimental chip was implemented in 1-mum CMOS and 8-b resolution at a sample rate of 85 me gasamples per second (MS/s) was obtained. Signal-to-noise plus distort ion (S/(N + D)) was 41 dB for an input sinusoid of 40 MHz.