A 6-NS 1-MB CMOS SRAM WITH LATCHED SENSE AMPLIFIER

This paper describes a I-Mb (256K x 4) CMOS SRAM with 6-ns access time . The SRAM, having a cell size of 3.8 mum x 7.2 mum and a die size of 6.09 mm x 12.94 mm, is fabricated by using 0.5-mum triple-polysilicon and double-metal process technology. The fast access time and low powe r dissipation of 52 mA at 100-MHz operation are achieved by using a ne w nMOS source-controlled latched sense amplifier and a data-output pre reset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle.