A 500-MEGABYTE S DATA-RATE 4.5M DRAM

Authors
KUSHIYAMA N OHSHIMA S STARK D NOJI H SAKURAI K TAKASE S FURUYAMA T BARTH RM CHAN A DILLON J GASBARRO JA GRIFFIN MM HOROWITZ M LEE TH LEE V
Citation
N. Kushiyama et al., A 500-MEGABYTE S DATA-RATE 4.5M DRAM, IEICE transactions on electronics, E76C(5), 1993, pp. 830-838
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEICE transactions on electronics → ACNP
ISSN journal
09168524
Volume
E76C
Issue
5
Year of publication
1993
Pages
830 - 838
Database
ISI
SICI code
0916-8524(1993)E76C:5<830:A5SD4D>2.0.ZU;2-V
Abstract
In order to improve system bus bandwidth, a novel, small-swing, synchr onous bus, which is based on a block-transfer-oriented protocol, has b een proposed. A 4.5M DRAM that interfaces to the bus directly and prov ides a 500-megabyte/s data rate has been developed.