A CURRENT-CONTROLLED LATCH SENSE AMPLIFIER AND A STATIC POWER-SAVING INPUT BUFFER FOR LOW-POWER ARCHITECTURE

This paper describes two new power-saving schemes for high-performance VLSI's with a large-scale memory and many interface signals. One is a current-controlled latch sense amplifier that reduces the power dissi pation by stopping sense current automatically. This sense amplifier r educes power without degrading access time compared with the conventio nal current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces dc current in interface circuits re ceiving TTL-high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM.