DONT CARE SET SPECIFICATIONS IN COMBINATIONAL AND SYNCHRONOUS LOGIC-CIRCUITS

We present a unified framework for the specification and computation o f don't care conditions for combinational and synchronous multiple-lev el digital circuits. We characterize such circuits in terms of graphs, logic functions and don't care conditions induced by the external and internal interconnections. We model the replacement of a gate in a sy nchronous logic network by a perturbation of the corresponding logic f unction, and show that the don't care conditions for the gate optimiza tion represent the bound on this perturbation. We present algorithms t o compute such don't care conditions in both the combinational and syn chronous case. We comment on the implementation of the algorithms and on the experimental results.