ION-BEAM-INDUCED CHARGE-COLLECTION IMAGING OF CMOS ICS

Charge collection regions of the Sandia TA670 16-Kbit SRAM have been d irectly imaged using a technique we call ion-beam-induced charge-colle ction (IBICC) imaging. During the IBICC measurement, the integrated ci rcuit is connected through its power (V(DD)) or ground (V(SS)) pins to a charge sensitive preamp whose output is pulse-height analyzed while the IC is exposed to a scanned 0.1-mum resolution microbeam of heavy ions. The IC, in effect, functions as its own detector of the magnitud e of charge collected following a heavy-ion strike. In this work, we e xamine the effect on IBICC imaging of varying power supply bias over a range of 0 to 15 V. Comparison of the IBICC image with the design lay out for this integrated circuit unambiguously identifies source and dr ain regions of n-channel transistors and drain regions of p-channel tr ansistors in the memory array. We were not able to image p-channel sou rce regions in either the V(DD) or V(ss) configuration. This result is clearly explained on the basis of the IC design. Comparison of IBICC images with previously measured single-event-upset (SEU) images of the TA670 provide a more complete understanding of the mechanisms that go vern single-event upset in this SRAM. IBICC holds great promise as a d iagnostic tool to quantify the underlying charge collection processes that are responsible for single event upset in complex integrated circ uits. It can also be applied to device failure analysis in a manner si milar to EBIC, with potentially higher resolution.