FAULT ANALYSIS ON (K-VALUED PLA STRUCTURE LOGIC-CIRCUITS(1))

Authors
WANG HM LEE CL CHEN JE
Citation
Hm. Wang et al., FAULT ANALYSIS ON (K-VALUED PLA STRUCTURE LOGIC-CIRCUITS(1)), IEICE transactions on fundamentals of electronics, communications and computer science, E76A(6), 1993, pp. 1001-1010
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic","Computer Applications & Cybernetics
Journal title
IEICE transactions on fundamentals of electronics, communications and computer science → ACNP
ISSN journal
09168508
Volume
E76A
Issue
6
Year of publication
1993
Pages
1001 - 1010
Database
ISI
SICI code
0916-8508(1993)E76A:6<1001:FAO(PS>2.0.ZU;2-L
Abstract
This paper presents a general form and a set of basic gates to impleme nt (K+1)-valued PLA structure logic circuits. A complete fault analysi s on the proposed circuit has been done and it is shown that all fanou t stem faults can be collapsed to branch faults. A procedure for fault collapsing is derived. For any function implemented in the (K+1)-valu ed circuit, the number of remaining faults is smaller than that of the 2-valued circuit after the collapsing, where the value of K is depend ent on the number of outputs and the assignment of the OR plane of the 2-valued logic circuit.