SYNTHESIS METHODS FOR FIELD-PROGRAMMABLE GATE ARRAYS

Field programmable gate arrays (FPGA's) reduce the turn-around time of application-specific integrated circuits from weeks to minutes. Howev er, the high complexity of their architectures makes manual mapping of designs time consuming and error prone thereby offsetting any turnaro und advantage. Consequently, effective design autontation tools are ne eded to reduce design time. Among the most important is logic synthesi s. While standard synthesis techniques could be used for FPGA's, the q uality of the synthesized designs is often unacceptable. As a result, much recent work has been devoted to developing logic synthesis tools targeted to different FPGA architectures. The paper surveys this work- The three most popular types of FPGA architectures are considered, na mely those using logic blocks based on lookup-tables, multiplexers and wide AND/OR arrays. The emphasis is on tools which attempt to minimiz e the area of the combinational logic part of a design since little wo rk has been done on optimizing performance or routability, or on synth esis of the sequential part of a design. The different tools surveyed are compared using a suite of benchmark designs.