A MULTIPROCESSOR ARCHITECTURE FOR VITERBI DECODERS WITH LINEAR SPEEDUP

A family of multiprocessor architectures implementing the Viterbi algo rithm is presented. The family of architectures is shown to be capable of achieving an increase in throughput that is directly proportional to the number of processors when the number of processors is smaller t han the constraint length nu of the code. The hardware utilization and the depth of the pipelining available inside each processor are also shown. An architecture with (nu - 1) processors is found to be particu larly advantageous, since it results in the maximum speedup and the si mplest interconnection structure.