FULL CMOS VIDEO LINE-LOCKED PHASE-LOCKED LOOP SYSTEM

Authors
RODDA WE CAMPBELL ER SAUER DJ MAYWEATHER WT DELLOVA F
Citation
We. Rodda et al., FULL CMOS VIDEO LINE-LOCKED PHASE-LOCKED LOOP SYSTEM, IEEE transactions on consumer electronics, 39(3), 1993, pp. 496-503
Citations number
NO
Categorie Soggetti
Telecommunications,"Engineering, Eletrical & Electronic
Journal title
IEEE transactions on consumer electronics → ACNP
ISSN journal
00983063
Volume
39
Issue
3
Year of publication
1993
Pages
496 - 503
Database
ISI
SICI code
0098-3063(1993)39:3<496:FCVLPL>2.0.ZU;2-Z
Abstract
A CMOS PLL system for generation of a television line-locked clock in the frequency range 25 MHz to 40 MHz is described. The PLL system is d esigned for use as a generic building block with large scale CMOS vide o signal processing integrated circuits. The development of a custom t est chip version of the PLL system is reported.