This paper describes the design and performance of a 8 GHz MMIC MESFET
power limiter. This limiter incorporates a special gate biasing schem
e and makes use of appropriate load conditions which reduce the unexpe
cted phase variations experienced by the signal through the device. Me
asured performances (phase variations less than 8-degrees over a 22 dB
input power range) are found to be in agreement with the theoretical
ones obtained from large signal simulations.