HIGH-LEVEL MODELING AND SYNTHESIS OF COMMUNICATING PROCESSES USING VHDL

The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a mor e specialized model, the behavior FSMs (BFSMs), for synthesis. The sim ulation semantics of VHDL presents challenges in describing behavior w ithout overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level s ynthesis and describes how we solved these problems in PUBSS.