OPTIMIZING GETTERING CONDITIONS FOR VLSI CHIPS USING SIMPLE YIELD MODEL

Conditions of an effective gettering procedure for VLSI processing are investigated by means of analytical simulation. The effectiveness of a gettering procedure is judged from the yield of VLSI where the densi ty of heavy metal impurities and gettering capability are varied in a wide range. As a result, the yield of VLSI drops seriously by the nega tive roles of gettering procedure. They are wafer warpage and dislocat ion propagation from a gettering site region to a device area, both of which are introduced by the gettering procedure itself. Consequently, it becomes clear that profitable gettering effects are obtained in th e VLSI processes only when the density of heavy metal impurity to be r emoved is not too high.