SIMD-SYSTOLIC ARCHITECTURE AND VLSI CHIP FOR COMPUTING THE DYNAMIC TIME-WARPING ALGORITHM

A VLSI architecture, which exhibits both SIMD and systolic behaviour f or computing the dynamic time-warping (DTW) algorithm is presented. Su ch an architecture is well-suited for VLSI implementation because of i ts regular structure and small number of input/output. Currently, base d on a 1.2 mum CMOS technology, a SIMD-systolic data-path chip has bee n designed and fabricated for computing the DTW algorithm. It is funct ionally correct and packaged as a 68-pin PGA chip. With such a chip, a 20000-word real-time DTW-based speech recognition system is achievabl e.