A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter

This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter . A power dissipation of 250 mW from a single 5 V supply is achieved using a radix = 2 pipeline architecture. Linearity and full-scale errors are remo ved through self-calibration and digital correction with on-chip circuitry. a novel single-ended to differential sample and hold stage is proven to ha ve very good single-ended input performance up to the Nyquist frequency, Th e total silicon area is 3.2 x 3.1 mm(2) in a 0.7 mu m CMOS process. Several circuit techniques used in this design together with experimental results are presented.