An analog background calibration technique for time-interleaved analog-to-digital converters

Authors
Dyer, KC Fu, DH Lewis, SH Hurst, PJ
Citation
Kc. Dyer et al., An analog background calibration technique for time-interleaved analog-to-digital converters, IEEE J SOLI, 33(12), 1998, pp. 1912-1919
Citations number
34
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
33
Issue
12
Year of publication
1998
Pages
1912 - 1919
Database
ISI
SICI code
0018-9200(199812)33:12<1912:AABCTF>2.0.ZU;2-3
Abstract
Analog background calibration using adaptive signal processing, an extra ch annel, and mixed signal integrators matches the offsets and gains of time-i nterleaved channels in a 10-b 40-Msample/s pipelined analog-to-digital conv erter. With monolithic background calibration, the peak signal-to-noise-and -distortion ratio is 58 dB, and power dissipation is 650 mW from 5 V. The a ctive area is 47 mm(2) in 1-mu m CMOS.