A 400-Msample/s, 6-b CMOS folding and interpolating ADC

A 400-Msample/s, 6-bit CMOS folding and interpolating analog-to-digital con verter (ADC) is described. A low-impedance current-mode approach is adapted , Current-division interpolation incorporated within the folders allows fas t operation and is compatible with low supply voltages, This interpolation scheme, together with a short aperture comparator, gives good performance f or input frequencies up to one-quarter of the sampling rate without using a sample and hold. For simplicity, the ADC uses only a single clock and its complement. The device is implemented in a 0.5-mu m BICMOS technology using only CMOS devices. The converter occupies 0.6 mm(2) and dissipates 200 mW from a 3.2-V supply.