A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal

In many wireless applications, it is necessary to demodulate and digitize f requency or phase modulated signals. Most commonly, this is done using sepa rate frequency discrimination and analog-to-digital (A/D) conversion. In lo w-cost IC technologies, such as CMOS, precise analog frequency discriminati on is not practical, so the A/D conversion is usually performed in quadratu re or at a nonzero intermediate frequency (IF) with digital frequency discr imination. While practical, the approach tends to require complicated A/D c onverters, and accuracy is usually limited by the quality of the A/D conver sion. This paper presents an alternative structure, referred to as a delta- sigma frequency-to-digital converter (Delta Sigma FDC), that simultaneously performs frequency demodulation and digitization, The Delta Sigma FDC is s hown to offer high-precision performance with very low analog complexity, A prototype of the key component of the Delta Sigma FDC has been fabricated in a 0.6 mu m, single-poly, CMOS process. The prototype achieved 50 kSample /s frequency-to-digital conversion of a 10 MHz frequency-modulated signal w ith a worst case signal-to-noise-and-distortion ratio of 85 dB and a worst case spurious-free dynamic range of 88 dB.