A 4,25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture

A single-chip 4.25-Gb/s 32:1, 1:32 transceiver, as specified in the emergin g American National Standards Institute fiber channel standard, has been de veloped using 0.25-mu m CMOS technology, Newly developed features contribut ing to the achievement of 4.25-Gb/s operations include: 1) an asynchronous tree-type 1:8 demultiplexer, 2) an 8-10 bit parallel-to-parallel frequency conversion circuit, and 3) comma detection and word alignment logic, The tr ansceiver consumes 600 mW in 4.25-Gb/s operations with a 2.5 V supply, This design helps achieve higher speed operations and only half the power dissi pation of the fastest previously reported CMOS fiber channel design that in cludes an 8B10B encoder and a 10B8B decoder.