This paper presents a 115-mW Global Positioning System radio receiver that
is implemented in a 0.5-mu m CMOS technology. The receiver includes the com
plete analog signal path, comprising a low-noise amplifier, I-Q mixers, on-
chip active filters, and 1-bit analog-digital converters. In addition, it i
ncludes a low-power phase-locked loop that synthesizes the first local osci
llator. The receiver achieves a 2.8-dB noise figure (prelimiter), a 56-dB s
purious-free dynamic range, and a 17-dB signal-to-noise ratio for a noncohe
rent digital back-end implementation when detecting a signal power of -130
dBm at the radio-frequency input.