High-level power modeling, estimation, and optimization

Silicon area, performance, and testability have been, so far, the major des ign constraints to be met during the development of digital very-large-scal e-integration (VLSI) systems. In recent years, however, things have changed ; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal com puting devices and wireless communication systems, which demand high-speed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of high-end products to keep power under contro l, due to the increased costs of packaging and cooling this type of devices . Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of low-p ower VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization t echniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appe ared in the recent literature.