Microprocessor power estimation using profile-driven program synthesis

This paper presents a new approach for estimating power dissipation in a hi gh performance microprocessor chip. A characteristic profile (including par ameters such as the cache miss rate, branch-prediction miss rate, pipeline stalls, instruction mix, and so on) is first extracted from the application programs. Mixed-integer linear-programming and heuristic rules are then us ed to gradually transform a generic program template into a fully functiona l program. The synthesized program exhibits the same characteristics (and h ence the same performance and power-dissipation behavior), yet it has an in struction trace that is orders of magnitude smaller than the initial trace. The synthesized program is subsequently simulated on a register-transfer-l evel description of the target microprocessor to provider the power-dissipa tion value. Results obtained for Intel's Pentium professor executing standa rd benchmark programs show a simulation-time reduction of three to five ord ers of magnitude.