Partial-scan delay fault testing of asynchronous circuits

Asynchronous circuits operate correctly only under timing assumptions. Henc e testing those circuits for delay faults is crucial, Previous work has sho wn that full-scan delay-fault testing of asynchronous circuits is feasible. In this work, we tackle the problem of partial-scan testing, which require s test-pattern generation an a sequential circuit, We show how this problem can be effectively reduced to a classical problem of stuck-at test-pattern generation for a related combinational circuit. The reduction is done in t hree steps. The first step reduces testing of an asynchronous sequential ci rcuit, by using a partial-scan approach, to testing an object called an asy nchronous net, in which feedback is allowed only inside asynchronous memory elements. We then decompose the problem of testing asynchronous nets into that of initializing memory elements (the second step), followed by robust path delay fault testing (the third step). We provide effective procedures to solve both the initialization and the test-pattern generation problem. T he technique is complete, automated, and requires only partial scan of some memory element outputs.