In this paper it will be shown that polysilicon encapsulated local oxi
dation of silicon (PE-LOCOS) is a feasible lateral isolation technique
for quarter-micron or smaller complementary metal-oxide-semiconductor
(CMOS) technologies. This isolation technique features limited proces
s complexity and very good manufacturability and reproducibility, toge
ther with excellent bird's beak and active area dimension control. Ele
ctrical measurements performed on perimeter intensive gate oxide capac
itors and diodes show no isolation-edge-related degradation; which is
confirmed by Raman spectroscopy and emission microscopy measurements.
Transistor narrow-channel data from devices fabricated with PE-LOCOS a
re presented and discussed.