IDENTIFICATION OF GRAIN-BOUNDARY TRAP PROPERTIES USING 3-LEVEL CHARGE-PUMPING TECHNIQUE IN POLYSILICON THIN-FILM TRANSISTORS

The grain-boundary trap properties in polysilicon thin film transistor s (poly-Si TFTs) are evaluated using the three-level charge-pumping (3 CP) technique. By measuring the 3CP current with various fall times, w e can obtain the grain-boundary trap distribution for each time consta nt window. The 3CP current versus step voltage characteristics indicat e that the total change of 3CP currents drastically increase as the fa ll time decreases and as the step time increases. The large change of 3CP current indicates that a large number of grain-boundary traps (D-g b greater than or equal to 4 x 10(11) eV(-1). cm(-2)) exist in the upp er half of the band gap in the n-channel TFTs. The grain-boundary trap density is derived from the step voltage dependence of the 3CP curren t. The influence of process temperature on trap properties is examined using the 3CP technique.