Y. Kawaguchi et al., 0.8-MU-M CMOS PROCESS COMPATIBLE 60V-100M-OMEGA-CENTER-DOT-MM(2) POWER MOSFET ON BONDED SOI, JPN J A P 1, 36(3B), 1997, pp. 1513-1518
In the present paper, we propose high voltage lateral power metal-oxid
e-semiconductor field effect transistor (MOSFET) on silicon on insulat
or (SOI), using the pure 0.8 mu m complementary metal-oxide-semiconduc
tor (CMOS) processes without diffusion self-alignment. The measured sp
ecific on-resistance of the developed lateral power n-channel MOSFET (
NMOSFET) was 100 m Ohm.mm(2) and breakdown voltage was 60 V. The fabri
cated device attains its on-resistance comparable to that of diffusion
self-align MOSFET (DMOSFET). It also achieves high side switch operat
ion by a reasonable cost, and can be integrated with Bipolar CMOS (BiC
MOS) circuits and micro processing unit (MPU). Compatibility of the de
veloped MOSFET to these low voltage circuits are demonstrated. Further
more, we show that the MPUs and BiCMOS analog circuit on SOI is suitab
le for high temperature operation.