PROPOSAL OF A SINGLE-TRANSISTOR-CELL-TYPE FERROELECTRIC MEMORY USING AN SOI STRUCTURE AND EXPERIMENTAL-STUDY ON THE INTERFERENCE PROBLEM INTHE WRITE OPERATION

A single-transistor-cell-type ferroelectric random access memory (FRAM ) which consists of an array of metal-ferroelectric-semiconductor fiel d effect transistors (MFSFETs) is proposed. In order to minimize the i nterference problem in the ''write/read'' operation, use of a silicon- on-insulator (SOI) structure is proposed, as well as optimizing the wr ite and read methods partly using experimental results for ferroelectr ic capacitors. A key method for avoiding the interference problem is t o generate a compensation pulse with a 1/3 amplitude and opposite pola rity in the next timing to each write pulse. It is concluded from thes e considerations that the proposed structure is promising for use as a single-transistor-cell-type FRAM, if the electrical properties of a f erroelectric film on a Si substrate is as good as that on a Pt electro de.