Development of three-dimensional unstructured mesh generator for the semiconductor process simulation

This paper reports the algorithm and its application of the three-dimension al mesh generator to the simulation of the semiconductor process. The devel oped mesh generator takes node insertion, node elimination and node relaxat ion schemes into account. Particularly, we have resolved a delooping proble m which in turn is encountered in the process of solving the moving boundar y problems. The quality factor of the generated meshes was found to improve from 0.16 to 0.31 when the above algorithms were applied. The mesh element s with poor quality could be upgraded by node relaxation. A recessed LOGOS structure was chosen to test the capability of our mesh generator. Calculat ions revealed that the compressive stress (about 3.2 x 10(12) dyne/cm(2)) i s distributed at the bottom concave corner of the thermal oxide. In additio n, the tensile stress (about -2.8 x 10(12) dyne/cm(2)) was generated at the convex earner of the silicon/oxide interface. It is noteworthy that the st ress is not generated at the intersection between the vertical concave corn er and the convex corner of the silicon/oxide interface.