Optimization and effects of device parameters on the memory cell operationof 1T/1C FRAM

Effects of device parameters on the memory cell operation of a 64 kb 1T/1C double level metal FRAM are evaluated by PSPICE tool using simplified linea r ferroelectric capacitor model. C-s, the capacitance for ferroelectric cap acitor switching, is linearized as P* over applied voltage on ferroelectric capacitor and C-n, the capacitance for ferroelectric non-switching is line arized as P<^> over the voltage. The simulated wave forms of plate line and bit line during cell operation using this model are well fitted with actua l wave forms during cell operation. Using this simulation tool, optimum dev ice parameter windows for a 64 kb 1T/1C double level metal FRAM cell operat ion are determined for the first time.