An algorithm-hardware-system approach to VLIW multimedia processors

Very Long Instruction Word (VLIW) processor architectures for multimedia ap plications are discussed from an algorithm, hardware and system based point of view. VLIW processors show high flexibility and processing power, as we ll as a good utilization of resources by compiler-generated code, but their exclusive exploitation of instruction level parallelism (ILP) decreases in efficiency as the degree of parallelism increases. This is mainly caused b y characteristics of multimedia algorithms, increasing wiring delays, compi ler restrictions, and a widening gap between on-chip processing speed and a vailable bandwidth to external memory. As new multimedia applications and s tandards continue to evolve (MPEG-4), the demand for higher processing powe r will continue. Therefore, parallel processing in all its available forms will have to be exploited to achieve significant performance improvements. We show that, due to the diminishing returns from a further increase in ILP , multimedia applications will benefit more from an additional exploitation of parallelism at thread-level. We examine how simultaneous multithreading (SMT), a novel architectural approach combining VLIW techniques with paral lel processing of threads, can efficiently be used to further increase perf ormance of typical multimedia workloads.