Fabrication of a dual-gate-controlled Coulomb blockade transistor based ona silicon-on-insulator structure

A new device structure for a single-electron-tunnelling transistor with a d ual-gate geometry has been fabricated based on the silicon-on-insulator str ucture prepared by SIMOX wafers. The split gate of the transistor is the lo wer-level gate and located similar to 20 nm above the inversion layer 2DEG active channel, which yields strong carrier confinement with a fully contro llable tunnelling potential barrier. The transistor operates at low tempera tures and exhibits single-electron tunnelling behaviour through a nano-size quantum dot. The Coulomb blockade oscillation is demonstrated at 15 mK and its periodicity is 16.4 mV in the upper gate voltage. For the nonlinear tr ansport regime, Coulomb staircases are clearly observed up to four current steps in the range of 100 mV drain-source bias. The I-V characteristics nea r zero bias display a typical Coulomb gap due to the one-electron charging effect. From the width of the blockade regime the dot capacitance is estima ted to be similar to 13 aF.