Dual damascene aluminum for 1-Gbit DRAMs

An advanced four-level interconnect process with three levels of minimum pi tch (0.35 mu m) dual damascene wiring is illustrated in this article. This novel process sequence is designed for a 1-Gbit DRAM (0.175 mu m generation ), and provides up to a 10% saving in chip area over a conventional three-l evel scheme. The electromigration and stress-migration performance of dual damascene Al is far superior to that of traditional RIE Al, alleviating the need to use Cu for improved reliability.