Low-voltage CMOS four-quadrant analogue multiplier for RF applications

CMOS four-quadrant multiplier consisting of four MOS transistors operating in the saturation region is introduced. The circuit exploits the quadratic relation between the current and voltage of the MOS transistor in saturatio n. Simulation results show that, for a supply voltage of 1.2 V, multiplicat ion can be performed at a frequency of 1.8 GHz, achieving better performanc es than a recently proposed similar architecture.