Performance of a context cache for a multithreaded pipeline

Hardware-multithreading is a technique in the design of high performance ma chines that is currently the subject of much active research. Such machines are characterised by the exploitation of instruction-level concurrency, ex tracted from simultaneously active multiple threads of control. The main ad vantage of this technique is in the elimination of performance-debilitating processor latencies, and the technique is therefore useful in the design o f both single-processor systems and parallel-processor systems. In this pap er we discuss the design and simulated performance of a novel operand-buffe ring system for a high-performance multithreaded pipelined uniprocessor. (C ) 1998 Elsevier Science B.V. All rights reserved.