Comparison of GaAs-based heterostructure n-channel transistors to Si in complementary processes

N-channel transistors are described with gate lengths of 0.6 and 0.3 mu m u sing complementary heterostructure FET (CHFET) technology. The drain curren t vs gate voltage curves fit a theoretical equation that includes effective mobility, peak electron velocity, and velocity overshoot. Using the drain current at the maximum gate-to-source voltage as a figure of merit, the CHF ET n-FETs are about four times faster than Si NMOS FETs with the same gate capacitance, gate width, and gate length, for gate lengths from 0.3-0.5 mu m. This speed ratio is also observed on real circuits with 0.6 mu m gate le ngths. This approximate speed ratio is expected to hold for gate lengths do wn to 0.1 mu m and below. The higher speed of CHFET comes directly from the higher electron mobility and peak electron velocity, which are respectivel y about four times higher and two times higher in CHFET than in Si. (C) 199 8 Elsevier Science Ltd. All rights reserved.