Performance analysis of a nonblocking ATM switch with a bufferless internal speedup fabric

In this paper, we study a non-blocking ATM switch with internal speedup. Mo difying the model developed in [X.R. Cao, The maximum throughput of a nonbl ocking space-division packet switch with correlated destinations. IEEE Tran sactions on Communications, 43 (5) (1995) 1898-1901], we can obtain the max imum throughput of such a switch; approximating the output process by a dis crete-time Markov modulated arrival, we can calculate the cell loss probabi lity at the output buffers. Our approach can be applied to switches with ar rival traffic having correlated destinations and asymmetric routing probabi lities. Simulation results illustrate that the approach is very accurate un der various traffic conditions. (C) 1998 Elsevier Science B.V. All rights r eserved.