Impact of ion energy on single-event upset

The impact of ion energy on single-event upset was investigated by irradiat ing CMOS SRAMs with low and high-energy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 mu m and integration densities from 16 Kbit to 1 Mbit. No significant differences we re observed between the low and high-energy single-event upset response. Th e results are consistent with simulations of heavy-ion track structures tha t show the central core of the track structures are nearly identical for lo w and high-energy ions. Three-dimensional simulations confirm that charge c ollection is similar in the two cases. Standard low energy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies d own to 0.5 mu m. We discuss implications for deep submicron scaling, multip le-bit upsets, and hardness assurance.